In the prior art, closed loop buffers using operational amplifiers have been used for high-precision buffering. Also, open loop buffers represented by an emitter follower are also in use.
However, for a closed loop buffer using an operational amplifier, because it has a feedback loop, it is hard to realize high speed of operation. Also, for such closed loop buffer, even when a bipolar processor is used, a commercially available general-purpose IC can only realize a settling time of about tens of ns, and it is hard to realize a settling time one order of magnitude shorter, that is, several ns. Also, in a closed loop buffer using a CMOS process, there is no way to realize a settling time of several ns. More specifically, an example of the general structure of a closed loop buffer using an operational amplifier as shown in FIG. 1 will be considered. A signal is input to the non-inverted input terminal of the operational amplifier, and the signal output is connected directly to the inverted input terminal to form a feedback with a feedback ratio of unity. In this way, a buffer with gain of 1-fold (voltage follower) is formed. In the operation of the operational amplifier, even when there is certain offset between the non-inverted input and the inverted input voltage, they are nearly equal to each other. Consequently, the output can completely follow the input, and the precision is rather high with respect to gain error, harmonic distortion, etc. On the other hand, usually, an operational amplifier consists of several or more transistors, and the same number of transistors are contained in the signal path. Also, since it is used with feedback applied on it, if no particularly special process is used, there is no way to expect a high speed of operation. In addition, if the DC gain of the amplifier is raised or the magnitude of the input differential transistor is increased to reduce the offset, the operation speed further falls. Even when an up-to-date CMOS process is used, it is still extremely hard to realize a settling time of a few ns for 12-bit operation.
On the other hand, for an emitter follower as an open loop buffer, although the speed is high, gain error and harmonic distortion are significant, so that the precision is poor. This will be considered in more detail. FIG. 2 is a diagram illustrating the general constitution of a source follower using NMOS transistor M1. The gate of M1 is for signal input; the drain is connected to the power source, and the source is terminated to ground via a constant-current source. The source is for signal output. Also, the back gate is hung on the source for improvement of precision. In this constitution, the input impedance is nearly infinitely high, and the output impedance is the reciprocal of gm (transconductance) of M1, and it is rather small. Also, the output sink current is up to I, the magnitude of the constant-current source, and the maximum level of the output source current is much larger than this. Consequently, a source follower is used as a buffer (buffer) with a high driving power. The input signal level and the output signal level divide the gate-source voltage (Vgs) of M1. However, since Vgs is normally nearly constant, it simply becomes a DC shift, and the output completely follows the input. Consequently, it becomes a buffer with a 1-fold gain. The DC shift itself is constantly offset, and there is no significant problem. In particular, there is no problem at all for application with AC coupling, etc.
Now, the case when this type of source follower drives a switched capacitor circuit or another capacitive load will be considered. In this case, because the output current is zero when the output voltage is in a completely settled state, current I of the constant-current source all flows through transistor M1. In this case, current I becomes a function of gate-source voltage (Vgs), drain-source voltage (Vds) and body (back gate)-source voltage (Vbs) of M1. That is, current I can be represented by Equation 1.
[Mathematical Formula 1]I=F(Vgs, Vds, Vbs)  (1)
Assuming that this current I is constant, in order for Vgs to be constant, one may just set Vds constant and Vbs constant. Now, since the back gate is hung on the source, Vbs=0 all the time. However, since the drain is hung on the power source (constant), the output signal (voltage on the source) varies following the input signal, and Vds varies nearly proportional to it. Sensitivity of current I with respect to Vds is not so high, and I can be determined nearly with Vgs. However, if variation in the input signal is high, the influence of variation in Vds cannot be ignored. That is, in the aforementioned relationship equation, when I is constant, Vds varies following the input signal, so that there is certain variation in Vgs, too. Consequently, gain error takes place. Also, because the signal dependence of Vgs is not completely linear, harmonic distortion takes place in the output. In a circuit with the constitution shown in FIG. 2, there is only one transistor contained in the signal path. Consequently, a preferable high-speed operation is fundamental. However, as aforementioned, there is a problem with respect to precision.
The above discussion applies in the same way on a source follower using a PMOS transistor shown in FIG. 3. In addition, it also applies on emitter followers using NPN, PNP, and other bipolar transistors.
Consequently, the objective of this invention is to provide a method for using a three-terminal device characterized by the fact that it can perform operation of a circuit containing a three-terminal device with a prescribed target, that is, at high speed and with high precision, as well as a type of circuit for using this method.
Another objective of this invention is to provide a method for reducing the Early effect component characterized by the fact that it can perform operation of a circuit containing a three-terminal device with a prescribed target, that is, at high speed and with high precision, as well as a type of circuit for using said method.
Yet another objective of this invention is to provide a method and circuit of a signal buffer using the Early effect component reducing method.
In addition, yet another objective of this invention is to provide various types of signal processing circuits using said buffer circuit.